Can VHDL and Verilog be enhanced for FPGAs?

Ada, a highly tightly typed and densely typed hardware description language, is where VHDL got its start. VHDL is far more verbose than Verilog, another HDL, as a result of the language requirement, which also increases the number of self-documenting designs. Strong typing in VHDL makes ensuring that explicit datatype conversions, like going from a bit-vector to an integer, happen. VHDL is utilized in electronic design automation to express mixed-signal and digital systems, such as integrated circuits and FPGA series like Zynq-7000 SoC, FPGA Spartan-7, Artix-7 FPGA, and Virtex-7 FPGAs. The semantics of the VHDL language were created to be exceedingly straightforward and clear. VHDL designs are compact, increasing the functionality of swiftly switching between tools. There is no need to be concerned about racial difficulties as a result.

fpga circuit board

The IEEE standard 1164 is mostly used in the VHDL design, and the Math and Numeric packages are also utilized to increase the language’s usefulness. VHDLs are tool-dependent and lack facilities for monitoring or simulation control. Because VHDL types are user-defined and lack an integrated simulation control, debugging design issues is more challenging and requires the use of interactive GUIs.

History development of VHDL

Although the entire FPGA community is making a lot of effort, this work is difficult to finish because of the nature of FPGAs. To understand why this is the case, it is necessary to look at the original design goals of FPGAs. The FPGA firm Xilinx was founded in 1984, a full year after the release of VHDL. In the beginning, the US military developed VHDL as a way to precisely describe how Application Specific Integrated Circuits (ASICs) function. Xilinx advertised FPGAs as a way to replicate ASICS’ activities without having to first manufacture them. VHDL was already being used by ASIC engineers, therefore Xilinx’s tools naturally supported it.

HDL is difficult to use because it tries to map a circuit’s behavior at the Register Transfer Level (RTL). This happens when data, in the form of electronic signals, passes through a sequence of logical gates and then flows from one register to the next within a predetermined period known as a clock cycle. In a single ASIC, the designer uses VHDL to determine how billions of these signals should move throughout each clock cycle. It naturally takes them a long time to appropriately simulate and debug FPGA designs as only experts can use it.

What is Verilog?

Hilo, an obsolete hardware description language, and the C programming languages are where Verilog’s roots may be found. Because it includes all recognized data types, it is an extremely constrained and weakly typed language. At the bit-level, the datatypes are displayed. Strings and Verilog can be combined. other data types. The simulation semantics in Verilog are less exact than those in VHDL.

Verilog offers developers a great deal of flexibility, but if coding conventions are broken, race scenarios could ensue from ambiguity. The reusability function of packages must be provided, however, due to the language’s limited scope and poor packaging ability, this is a very challenging task.

Basic simulation control commands are provided by Verilog to aid in system functioning. Due to the pre-defined system tasks and straightforward data formats in Verilog, programmers frequently use command-line or batch simulations. Waveforms from the simulation can also be used for debugging.

History development of Verilog

In 1990, Gateway Design Automation Inc. was acquired by Cadence Design System, one of the industry’s biggest suppliers of engineering and electronic design technology. Cadence recognized the advantages of Verilog and realized that if it remained a closed language, standardization pressure would eventually push people to convert to VHDL. To put the Verilog documentation into the public domain, Cadence established the Open Verilog International (OVI) (now known as Accellera) in 1991. It was then submitted to the IEEE, where it was approved as IEEE standard 1364-1995, also known as Verilog-95.

Verilog-2001, also known as IEEE standard 1364-2001, was produced as a result of Verilog-95 extensions that were once again submitted to the IEEE in 2001. The extensions solved certain issues that users have found with the Verilog-95. One of the main enhancements was the ability for signed variables (in 2.s complement). The majority of design tools currently available support Verilog-2001, the language’s current standard edition.

2005 saw the publication of Verilog-2005 (IEEE Standard 1364-2005), which contains a few minor corrections and modifications. 2005 also saw the introduction of System Verilog, a superset of Verilog that includes many new features and abilities to aid in design verification. The SystemVerilog and Verilog language standards were combined in 2009 to create SystemVerilog 2009 (IEEE Standard 1800-2009), one of the most commonly used languages for IC design and verification today. The 2013-released Xilinx® Vivado Design Suite for FPGA design and verification supports SystemVerilog.

Conventional FPGA Design Tools

Hardware description languages (HDLs), such as VHDL and Verilog, developed as the main languages for defining the algorithms that execute on the FPGA chip over the first 20 years of FPGA development. These low-level languages incorporate some of the advantages of existing textual languages with the understanding that you are building a circuit on an FPGA. To use the resulting hybrid syntax, signals from external I/O ports must be mapped or connected to internal signals before being passed to the functions that house the algorithms.

These processes can make references to other FPGA-based functions while they are running simultaneously. However, it is difficult to understand the true parallel nature of the job execution on an FPGA due to a sequential line-by-line flow. Although HDLs share some characteristics with other textual languages, they also differ significantly because they are built on a dataflow model, in which I/O is linked to several function blocks through signals.

HLS tools

If we could use these high-level languages, like C, for FPGA designs, we could get the performance advantages of specialized hardware without writing HDL. Since the 1990s, High-Level Synthesis (HLS) technologies have been working toward this goal. Since then, HLS tools have significantly improved and are supported by the industry. Industrial tools include Vivado HLS from AMD (previously Xilinx), the Intel HLS Compiler, and SmartHLS from MicroChip.

These HLS compilers are typically not perfect because these languages were designed to be turned into lists of instructions rather than circuits. The great performance that FPGAs are known for can only be properly translated into a circuit in a small portion of C. Long chains of ‘if’ statements perform poorly, but ‘for’ loops can be translated correctly.

A new generation of tools that utilize both CPUs and FPGAs has been created as a result. The two could be merged in this configuration on a single chip known as a “system-on-chip” with shared memory. As an alternative, they can be separate chips linked together through a PCI interface. Both Intel’s OneAPI and AMD’s Vitis Unified Development environment employ this technique.

Tools specific to a domain

Another intriguing subject is tools that are domain-specific and produce designs specifically for certain uses. The machine learning industry, where FPGA technology has shown considerable promise, uses these technologies the most frequently. These tools typically provide the best architecture for a model from a well-known machine learning framework, such as PyTorch or TensorFlow.

This translates to the fact that FPGAs can be used by software developers without needing any technical expertise and still produce a good performance. Community resources for this include FINN and HLS4ML.


Throughout the history of the FPGA industry, several initiatives have been made to establish development languages that are superior to Verilog or VHDL. From community-based efforts to develop HDLs in more approachable programming languages to HLS tools that attempt to translate standard software code into high-performance hardware. The most successful advancement has been the creation of domain-specific tools that can produce effective FPGA designs for certain purposes, including machine learning.

These new tools and languages advance FPGA technology because they can produce FPGA-level performance with a great deal less effort during development. Sadly, they can only do so in certain circumstances. VHDL and Verilog still have a bright future because of their innate capacity to model circuits at the RTL level and their widespread industry use. The best thing that engineers can do is educate themselves on these HDLs while remaining receptive to new information and eager to participate in the development of these new tools. The FPGA community could expand as a result, and productivity might rise.

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